1) Field of the Invention
The present invention relates to a latch circuit, a 4-phase clock generator, and a receiving circuit, and particularly to a latch circuit, a 4-phase clock generator, and a receiving circuit which are used in radio communication technique such as IQ receiving method using 4-phase clock signals that have phases that are shifted by 90 degree.
2) Description of the Related Art
Radio waves are used for various applications. Much demand of usage of radio waves causes the shortage of frequency resources, and many signals are thereby present in a remarkably small frequency range. When signals are in such a situation, the signals often come under the inference of interference with near-by frequency and jamming signal called image signal. Consequently, a new technique comes to be required to eliminate this influence. An IQ receiving method is one of such techniques. In this method, phases of clock signals are shifted by 90 degree and the clock signals are used to compensate for an interference component between a target main signal and a jamming signal. On the other hand, in the field of portable terminals, lower power consumption in devices or circuits has been strongly desired along with spread and enhancement of the portable terminal.
There have been disclosed several 4-phase clock generators that generate clock signals with phases shifted by 90 degree. Some 4-phase clock generators use a plurality of RC filters or CR filters called polyphase filter. Some use a fixed delay block, and others acquire an output from an appropriate node in the DLL circuit. These 4-phase clock generators are suitable for applications in a single frequency or narrow frequency range, however, are not suitable for applications in a remarkably large frequency setting range such as a receiving terminal of TV broadcasting.
Some 4-phase clock generators, used for applications in a large frequency range, use a feature that a phase in an intermediate node in the 2-frequency-divider circuit is shifted by 90 degree for a phase of the final output signal. The 2-frequency-divider circuit is generally realized by interconnecting two latch circuits or latch circuits, as disclosed in IEEE Journal of Solid State Circuit, Unite States, 1997, volume 32, No. 1, pp. 62-69, “New Single-Clock CMOS Latches and Flip-flop with Improved Speed and Power Saving” by Jiren Yuan et al. In some latch circuits, a bipolar transistor and a constant current source are combined. However, a disadvantage of such latch circuits is that this configuration causes a current to always flow, and is not suitable for application which requires low power consumption such as portable terminal.
Some latch circuits, called inverter type, do not use a constant current source. FIG. 1 is a circuit diagram of a conventional inverter-type latch circuit, and FIG. 2 is a schematic of output waveforms of the conventional latch circuit shown in FIG. 1. The conventional latch circuit 2200 includes an input-timing-control MOS transistor 2201, a first input transistor 2202, a second input transistor 2203, and a pair of CMOS inverter circuits 1704 and 1705. The input-timing-control MOS transistor 2201, the first input transistor 2202, and the second input transistor 2203 are MOS transistors.
When a clock signal CK is input into the data input-timing-control MOS transistor 2201 and the clock signal CK transits from a relatively low potential level (hereinafter, “L level”) to a relatively high potential level (hereinafter, “H level”), if input data D of the first input transistor 2202 is at L level and input data DX of the second input transistor 2203 is at H level, output data Q of the second inverter circuit 1705, which is connected to the second input transistor 2203, gets to be at L level. The input data DX corresponds to inverted data of the data D.
At the same time, input data of the first inverter circuit 1704 connected to the first input transistor 2202 gets to be at L level, and therefore, output data QX of the first inverter circuit 1704 gets to be at H level. The output data QX corresponds to inverted data of the data Q. This state is maintained after the clock signal CK transits to L level until it transits to H level again.
When the clock signal CK transits to H level, the input data D is at H level and the input data DX is at L level, and therefore, the output data QX of the first inverter circuit 1704 gets to be at L level. At the same time, the input data of the second inverter circuit 1705 gets to be at L level, and therefore, the output data Q of the second inverter circuit 1705 gets to be at H level. This state is maintained until the clock signal CK transits from L level to H level next time.
However, the conventional latch circuit 2200 has some problems. In the conventional latch circuit 2200, the output data Q (or QX) of one inverter circuit 2204 (or 2205) transits from H level to L level, and then, the output data QX (or Q) transits from L level to H level due to the inverting operation of the other inverter circuit 1705 (or 1704). Therefore, as shown in FIG. 23, there is a time delay t between the timing of the transition from L level to H level and the timing of the transition from H level to L level. A problem is that a phase difference by one stage of inverter circuit in the latch circuit 2200 occurs between the output data Q and the output data QX. Further, another problem is that the duty ratios of the output data Q and QX are shifted from 50%, and fast operation or highly accurate phase generation is prevented.
There is still another problem. Even when such latch circuit 2200 is used to configure the 4-phase clock generator, it is difficult to accurately set the phase difference of the 4-phase clock signals at 90 degree, and unwanted components cannot be eliminated completely by the IQ receiving method. Consequently, the reception characteristics deteriorate.